時間：2014年7月8日（周二）上午10:30-11:30

　　地點：計算所4層446會議室

　　摘要

　　This presentation will talk about the use of multi-level cell (MLC) spin-transfer torque RAM (STT-RAM) in cache design of microprocessors and embedded systems. By saving two or more digital bits in>　　 

　　主講人簡介

　　Hai Li received B.S. and M.S. from Tsinghua University and Ph.D. from Purdue University. She is currently an Assistant Professor in the Department of Electrical and Computer Engineering at University of Pittsburgh. Before joining Pitt in Fall 2012, she has been with Polytechnic Institute of New York University for three years. Prior it, she worked with Qualcomm Inc., Intel Corp., and Seagate Technology. Prof. Li is a recipient of the National Science Foundation (NSF) Early Faculty (CAREER) award, the Defense Advanced Research Projects Agency (DARPA) Young Faculty Award (YFA), and several Best Paper Award and Best Paper Award Nominations at IEEE/ACM conferences. He has published more than 100 research papers in journals and refereed conference proceedings, in the area of EDA, computer architecture, VLSI circuit designs, and embedded systems.